AI-Assisted Memory Design Intern

About the Role

Work closely with foundation IP team and explore Artificial Intelligence (AI)-assisted and self-adaptive memory design techniques that leverage operating-condition awareness to dynamically optimize memory operation for improved performance, power efficiency, and yield.

Responsibilities

• Analyze conventional memory assist techniques and explore how AI/ML-driven learning and optimization can enhance control logic, supply modulation, boosted/negative voltages, and replica/tracking schemes.
• Investigate AI/ML-based techniques to analyze memory operating conditions, identify failure signatures, and predict robustness across voltage, temperature, process variation, timing, and parasitic effects.
• Explore self-timed, self-adaptive, and intelligent memory techniques that learn from operating conditions and dynamically optimize assist decisions for improved robustness, power, performance, and yield.
• Develop AI/ML-assisted monitoring, prediction, and adaptive control techniques for dynamically optimizing memory assist, voltage, timing, and read/write operations.
• Document, benchmark, and present the proposed self-adaptive memory architecture and key design insights.

Qualifications

• Pursuing a BS in EE, CE, Microelectronics, or related field (rising Junior/Senior).
• Coursework in Digital Integrated Circuits, Analog Circuit Design, VLSI Design, or Semiconductor Devices.
• Coursework in Machine Learning, Optimization, Data Analytics, Computational Methods or related courses.
• Basic understanding of CMOS circuit design and IC layout (DRC/LVS) concepts.
• Working knowledge of Python and basic ML concepts (regression, clustering).
• Comfort working with large datasets.
• Strong analytical and problem-solving ability.

Nice to Have

• Exposure to layout/schematic tools (Virtuoso, Calibre) or characterization tools (SiliconSmart, PrimeTime, Liberate)
• Interest in low-power IP for edge AI/IoT
• Strong passion, eagerness, and curiosity to learn and explore transistor-level circuit design.