AI-Assisted Foundation IP Development Intern

About the Role

Part of Foundation IP team on standard cell and memory compiler IP for edge AI SoCs — including using data analysis and ML to spot trends in characterization data and flag outliers early.

Responsibilities

• Support circuit design, spice/Monte Carlo simulation and layout of standard cells
• Perform layout tasks (placement, routing, DRC/LVS cleanup) for foundation IP
• Characterize standard cells (timing, power, noise) across PVT corners
• Run characterization flows using tools like Liberate
• Analyze characterization data using Python (pandas, scikit-learn) to find trends and outliers
• Build simple predictive models to flag likely failures and reduce simulation runs
• Help debug mismatches between simulated and characterized results
• Document findings and share with the IP team

Qualifications

• Pursuing a BS in EE, CE, Microelectronics, or related field (rising Junior/Senior)
• Coursework in digital logic, Analog, AI/ML, data Science, VLSI, or semiconductor devices
• Basic understanding of circuit design and IC layout (DRC/LVS) concepts
• Working knowledge of Python and basic ML concepts (regression, clustering)
• Comfort working with large datasets

Nice to Have

• Exposure to layout/schematic tools (Virtuoso, Calibre) or characterization tools (Liberate, Tempus)
• A class project applying ML to engineering or scientific data
• Interest in low-power IP for edge AI/IoT