Lead RTL Design Engineer

About The Role

• Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
• Managing external ASIC vendor through product development cycle.
• Work closely with PD team members for design closure to meet PPA goals.
• Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
• Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
• Debug silicon-level functional, timing, and power issues during bring up.

• Master’s degree in Computer Science, Electrical Engineering, or equivalent.
• Can work in a hybrid work environment. 
• 8-15 years of experience in delivering complex, high performance high quality RTL designs.
• Experience with Front End Chip integration and third-party IP integration.
• Demonstrated experience in networking, high-performance computing, machine learning or related fields.
• Proven track record of multiple silicon success.
• Experience collaborating and managing external vendors.
• Experience with designing/integrating  high speed IO.
• Networking stack experience including TCP/IP, RDMA and Ethernet.
• Knowledge of PCIe, CPU interfaces and Serdes technology.
• Working knowledge of scripting tools : Python, TCL.

Assets

• Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus.

 The base salary range for this position is $175,000 to $275,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.